![]() ![]() At a theoretical peak of 25.6 GB/s bandwidth per channel, this equates to a single access latency of 13.75 nanoseconds. Starting with the lowest data rate, the DDR5-3200A standard supports 22-22-22 sub-timings. It means that each data rate can cast a wide range of performance based on the quality of the silicon used. At the end of DDR3, and through DDR4, JEDEC introduced additional sub-timing specifications for each data rate - for each of the data rates, JEDEC has specified an ‘A’ fast standard, a ‘B’ common standard, and a ‘C’ looser standard – technically the looser standard is more applicable to higher capacity modules. It also has placeholders up to DDR5-8000, however the specifics of those standards are still a work in progress. Pivoting to DDR5, JEDEC has enabled standards ranging from DDR5-3200 to DDR5-6400. However recently, due to physical limitations, while data rate has been increasing, access latency has been roughly consistent. Moving from the early iterations of DRAM, both data access rates and single access latencies have improved. The combination of data rate and CAS Latency has been used to compare single access latency numbers for memory over the years. ![]() For latency calculations, we need both the data rate (3200 MT/s) and the CAS (24 clocks) to calculate the CAS in terms of nanoseconds, the real world latency (in this case, 15 nanoseconds). This means that in JEDEC’s DDR4 specification, the base DDR4-3200 metric allows for a 24-24-24 set of sub-timings. These are typically reported as CAS-tRCD-tRP with tRAS sometimes added on.
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